Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Wire Placement for Crosstalk Energy Minimization in Address Buses
Proceedings of the conference on Design, automation and test in Europe
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data coding for interconnect power and timing optimization has been introduced. In today's SoCs these techniques are not efficient anymore due to their codec complexity or to their unrealistic experimentations. Based on some realistic observations on interconnect delay and power estimation, the spatial switching technique [1] is proposed. It allows the reduction of delay and power consumption (including extra power consumption due to codecs) for on-chip buses. The concept of the technique is to detect all cross-transitions on adjacent wires and to decide if the adjacent wires are exchanged or not. Results show the spatial switching efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 5-mm bus and more if buses are longer.