Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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In this paper, we present some new crosstalk avoidance coding schemes devoted to on-chip busses. These schemes consist in encoding sequences of bits on each line of a bus transferring a packet in order to eliminate worst-case crosstalk patterns. They permit to improve the delay on the link at the cost of doubling the number of transmitted bits. The advantage of the presented solutions is that they have no wiring overhead, so they are independent from the bus bit-width. The coding schemes allow an increase of 50% of the data rate for a 1-mm bus. Moreover, the proposed solutions induce a direction in deepsubmicron noise that can be used to implement a noise-tolerant system.