Modeling magnetic coupling for on-chip interconnect
Proceedings of the 38th annual Design Automation Conference
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Wire Placement for Crosstalk Energy Minimization in Address Buses
Proceedings of the conference on Design, automation and test in Europe
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
| Hi-index | 0.00 |
Pulse-encoded buses, (i.e., in which a transition is encoded as a pulse) have recently emerged as an effective solution to solve crosstalk issues in global interconnects, since they suppress transitions in opposite directions by construction. As a side effect, this also reduces energy, since coupling capacitances in deep-submicron technologies are larger than ground capacitances. Furthermore, a single pulse consumes less energy than a conventional transition, because the limited length does not fully implies extra transitions since all input transitions are encoded with a pulse. This tradeoff leaves the issue of energy efficiency of pulsed buses an open problem, which we address in this work. We present an explorative analysis of the energy efficiency bounds of pulse encoded bus with respect to conventional level-signaled ones. More specifically, we provide a quantitative comparison of the two signaling modes under the same delay constraints, by accounting for the various bus devices (codecs, drivers, and receivers), under (i) the presence of process variations, and (ii) under different input switching activities transmitted on a bus, along with the impact of delay and pulse width.