Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Error-correction and crosstalk avoidance in DSM busses
Proceedings of the 2003 international workshop on System-level interconnect prediction
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized design of interconnected bus on chip for low power
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
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In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of trade-offs between bus delay, codec latency, power, area, and reliability. Simulation results, for a 1-cm 32-bit bus in a 0.18-$mu$m CMOS technology, show that 31 reduction in energy and 62 reduction in energy-delay product are achievable.