A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It is shown in this paper that the optimum position of interleaved repeaters for minimum delay and noise is not the midpoint as commonly practiced. A closed form solution for the optimum position has been derived in this paper and verified by simulation. Bi-directional buses with the optimum interleaved repeater position are compared to commonly used bi-directional buses and shown to provide an improvement of as much as 100% in both the propagation delay and bit-rate per unit area. The area of the induced noise pulse on victim lines is shown to be zero indicating that the aggressor lines are virtually static when optimum repeater positioning is used.