Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Digital CMOS Design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Computers and Electrical Engineering
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In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper, we address the problem of design space exploration of low-energy software bus encoding in embedded SoC design. Traditionally, finding a bus encoding that leads to a minimum energy consumption of bus has been an important research issue, but relatively little attention has been paid to the cost of software encoding implementation. In embedded system design, the memory space for storing the encoding information is strictly limited. Consequently, exploring the bus encoding implementation alternatives under such constraint becomes very necessary and/or useful. In this paper, we propose a systematic design space exploration algorithm for low-power bus encoding which completely eliminates the crosstalk delay. From experiments on a set of benchmark designs, the proposed algorithm was shown to consume 48% less power consumption on average over existing techniques with relatively little memory overhead.