Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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This paper describes a novel low-power coding methodology for buses. Ultra deep submicron technology and system-on-chip have resulted in a considerable portion of power consumption on buses, in which the major sources of the power consumption are the transition activities on the signal lines and the coupling capacitances of the lines. In addition, we enter an era of considering variation of the effective coupling capacitances. We address power reduction including these phenomena by using variable length coding. Experimental results show the effectiveness of our methodology.