DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
VGTA: Variation Aware Gate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
Parameterized block-based non-gaussian statistical gate timing analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A variation-aware low-power coding methodology for tightly coupled buses
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
SACI: statistical static timing analysis of coupled interconnects
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Statistical gate delay model for multiple input switching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analytical model for the impact of multiple input switching noise on timing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Speedpath prediction based on learning from a small set of examples
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Silicon feedback to improve frequency of high-performance microprocessors: an overview
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
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There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assume a Single Input Switching model. Our experiments show that SIS underestimates the mean delay of a stage by upto 20% and overestimates the standard deviation upto 26%. We also show that Multiple Input Switching has a greater impact on statistical timing, than regular static timing analysis. Hence, we propose a modeling technique for gate delay variability, considering MIS. Our model can be efficiently incorpo-rated into most of the statistical timing analysis frameworks. On average over all test cases, our approach underestimates mean delay of a stage by 0.01% and overestimates the standard deviation by only 2%, hence increasing the robustness to process variations. Our modeling technique is independent of the deterministic MIS model, and we show that its sensitivity to variations in the MIS model is small.