SACI: statistical static timing analysis of coupled interconnects

Authors:
Hanif Fatemi;Soroush Abbaspour;Massoud Pedram;Amir H. Ajami;Emre Tuncer
Affiliations:
University of Southern California, Los Angeles, CA;University of Southern California, Los Angeles, CA;University of Southern California, Los Angeles, CA;Magma Design Automation, Santa Clara, CA;Magma Design Automation, Santa Clara, CA
Venue:
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Year:
2006

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Abstract

Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a significant impact on both device (front-end of the line) and interconnect (back-end of the line) performance. Statistical static timing analysis techniques are being developed to tackle this important problem. Existing timing analysis tools divide the analysis into interconnect (wire) timing analysis and gate timing analysis. In this paper, we focus on statistical static timing analysis of coupled interconnects where crosstalk noise analysis is unavoidable. We propose a new framework for handling the effect of Gaussian and Non-Gaussian process variations on coupled interconnects. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as the line width, metal thickness, and dielectric thickness in the presence of crosstalk noise. To achieve this goal, we express the electrical parameters of the coupled interconnects in a first order (linear) form as function of changes in physical parameters and subsequently use these forms to perform accurate timing and noise analysis to produce the propagation delay and slew in the first-order forms. This work can be easily extended to consider the effect of higher order terms of the sources of variation. Experimental results show that the proposed method is capable of accurately predicting delay variation in a coupled interconnect line.