DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Guaranteed passive balancing transformations for model order reduction
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
NORM: compact model order reduction of weakly nonlinear systems
Proceedings of the 40th annual Design Automation Conference
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme
Proceedings of the 41st annual Design Automation Conference
A linear fractional transform (LFT) based model for interconnect parametric uncertainty
Proceedings of the 41st annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A quasi-convex optimization approach to parameterized model order reduction
Proceedings of the 42nd annual Design Automation Conference
SACI: statistical static timing analysis of coupled interconnects
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Crosstalk analysis in nanometer technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Parameterized model order reduction of nonlinear dynamical systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A practical method to estimate interconnect responses to variabilities
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A frequency-domain technique for statistical timing analysis of clock meshes
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parameterized model order reduction via a two-directional Arnoldi process
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Proceedings of the conference on Design, automation and test in Europe
Deep submicron interconnect timing model with quadratic random variable analysis
Proceedings of the conference on Design, automation and test in Europe
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
HORUS - high-dimensional model order reduction via low moment-matching upgraded sampling
Proceedings of the Conference on Design, Automation and Test in Europe
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
Performance-oriented parameter dimension reduction of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametrized model reduction based on semidefinite programming
Automatica (Journal of IFAC)
| Hi-index | 0.00 |
Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.