Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the difference between the nominal and perturbed circuit waveforms by calculating the moments in frequency-domain via efficient iterative method. The algorithm can be used to accurately reproduce the differential waveforms, or to provide efficient early estimates on the timing impact of the variabilities for RC networks.