Statistical gate delay model for multiple input switching

Authors:
Takayuki Fukuoka;Akira Tsuchiya;Hidetoshi Onodera
Affiliations:
Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan and JST, CREST
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

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Abstract

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). Most SSTA approaches assume a single input switching model and ignore the effect of MIS on gate delay. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in MAX operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations and experimental results show that the proposed method improves the error due to ignoring MIS.