The nature of statistical learning theory
The nature of statistical learning theory
An introduction to support Vector Machines: and other kernel-based learning methods
An introduction to support Vector Machines: and other kernel-based learning methods
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
On Silicon-Based Speed Path Identification
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
Silicon feedback to improve frequency of high-performance microprocessors: an overview
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Speedpath analysis based on hypothesis pruning and ranking
Proceedings of the 46th Annual Design Automation Conference
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Proceedings of the 2009 International Conference on Computer-Aided Design
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
Representative path selection for post-silicon timing prediction under variability
Proceedings of the 47th Design Automation Conference
On-die power grids: the missing link
Proceedings of the 47th Design Automation Conference
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Power grid effects and their impact on-die
Proceedings of the International Conference on Computer-Aided Design
Data mining in design and test processes: basic principles and promises
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In high performance designs, speed-limiting logic paths (speedpaths) impact the power/performance trade-off that is becoming critical in our low power regimes. Timing tools attempt to model and predict the delay of all the paths on a chip, which may be in the millions. These delay predictions often have a significant error and when silicon is measured there is a large variation of path delays as compared to the prediction of the tools. This variation may be caused by process, environmental or other effects that are often unpredictable. It is therefore desirable to use early silicon data to better predict and model potential speedpaths for subsequent silicon steppings. In this paper, we present a novel machine learning-based approach that uses a small number of identified speedpaths to predict a larger set of potential speedpaths, thus significantly enhancing the traditional timing prediction flows post-silicon. We demonstrate the feasibility of this approach and summarize our findings based on the analysis of silicon speedpaths from a 65nm P4 microprocessor.