Convex Optimization
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Efficient computation of the worst-delay corner
Proceedings of the conference on Design, automation and test in Europe
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
Speedpath prediction based on learning from a small set of examples
Proceedings of the 45th annual Design Automation Conference
A framework for block-based timing sensitivity analysis
Proceedings of the 45th annual Design Automation Conference
Silicon feedback to improve frequency of high-performance microprocessors: an overview
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Proceedings of the 2009 International Conference on Computer-Aided Design
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
The clock frequency of a digital IC is limited by its slowest paths, designated by speedpaths. Given the extreme complexity involved in modeling modern IC technologies, often speedpath predictions provided by timing analysis tools are not correct. Therefore, several practical techniques have recently been proposed for design debugging, that combine silicon stepping of improved versions of a circuit with subsequent correlation between measured and predicted data. Addressing these issues, this paper proposes a set of techniques that enable the designer to obtain reduced subsets of paths, guaranteed to contain all the speedpaths of a given circuit or block. Such subsets can be computed either from timing models, prior to fabrication, or incorporating actual delay measurements from fabricated instances.