Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Convex Optimization
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
"AU: Timing Analysis Under Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On the need for statistical timing analysis
Proceedings of the 42nd annual Design Automation Conference
A linear-time approach for static timing analysis covering all process corners
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A framework for block-based timing sensitivity analysis
Proceedings of the 45th annual Design Automation Conference
Effective corner-based techniques for variation-aware IC timing verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
A unified multi-corner multi-mode static timing analysis engine
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A fast approach for static timing analysis covering all PVT corners
Proceedings of the 48th Design Automation Conference
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Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.