Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Convex Optimization
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
"AU: Timing Analysis Under Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient computation of the worst-delay corner
Proceedings of the conference on Design, automation and test in Europe
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Handling intra-die variations in PSTA
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Unifying functional and parametric timing verification
Proceedings of the great lakes symposium on VLSI
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Traditional integrated circuit timing sign-off consists of verifying a design for a set of carefully chosen combinations of process and operating parameter extremes, referred to as corners. Such corners are usually chosen based on the knowledge of designers and process engineers, and are expected to cover the worst-case fabrication and operating scenarios. With increasingly more detailed attention to variability, the number of potential conditions to examine can be exponentially large, more than is possible to handle with straightforward exhaustive analysis. This paper presents efficient yet exact techniques for computing worstdelay and worst-slack corners of combinational and sequential digital integrated circuits. Results show that the proposed techniques enable efficient and accurate detection of failing conditions while accounting for timing variability due to process variations.