Introduction to mathematical logic; (3rd ed.)
Introduction to mathematical logic; (3rd ed.)
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Full chip false timing path identification: applications to the PowerPCTM microprocessors
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 39th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
False Path Aware Timing Yield Estimation under Variability
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Effective corner-based techniques for variation-aware IC timing verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient algorithm to verify generalized false paths
Proceedings of the 47th Design Automation Conference
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path sensitization in critical path problem [logic circuit design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computation of floating mode delay in combinational circuits: practice and implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a unified modeling framework for timing verification of IC designs that, through an elegant SMT-based formulation, seamlessly integrates functional timing analysis and parametric delay modeling. Such framework enables accurate timing verification by simultaneously ignoring false paths and accounting for process variability. By casting the timing verification problem as a general SMT instance it is possible to benefit from the continuous advances in performance and robustness of modern SMT engines. The proposed framework is validated for a representative set of benchmarks, using Microsoft's Z3 SMT solver.