Unifying functional and parametric timing verification
Proceedings of the great lakes symposium on VLSI
Functional timing analysis made fast and general
Proceedings of the 49th Annual Design Automation Conference
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
Automatic test pattern generation for delay defects using timed characteristic functions
Proceedings of the International Conference on Computer-Aided Design
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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An important aspect of the critical path problem is deciding whether a path is sensitizable. Three new path sensitization criteria are proposed in a general framework. Other path sensitization criteria can be presented in the same framework, enabling them to be compared with each other. An approximate criterion is also proposed and used to develop an efficient critical path algorithm for combinational circuits