Full chip false timing path identification: applications to the PowerPCTM microprocessors

Authors:
J. Zeng;M. Abadir;J. Bhadra;J. Abraham
Affiliations:
EDA Tools and Methodology, Motorola ASP Somerset Design Center, Austin, TX and Computer Engineering Research Center, The University of Texas at Austin, Austin, TX;EDA Tools and Methodology, Motorola ASP Somerset Design Center, Austin, TX;EDA Tools and Methodology, Motorola ASP Somerset Design Center, Austin, TX and Computer Engineering Research Center, The University of Texas at Austin, Austin, TX;Computer Engineering Research Center, The University of Texas at Austin, Austin, TX
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2001

Timing analysis with known false sub graphs

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Detecting false timing paths: experiments on PowerPC microprocessors

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Removing user specified false paths from timing graphs

Proceedings of the 37th Annual Design Automation Conference
Transistor level synthesis and hierarchical timing optimization for cmos combinational circuits

Transistor level synthesis and hierarchical timing optimization for cmos combinational circuits
Critical Path Identification and Delay Tests of Dynamic Circuits

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Classification and identification of nonrobust untestable path delay faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Hi-index	0.00