Path verification using Boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
A new approach to the use of satisfiability in false path detection
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Efficient identification of multi-cycle false path
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On Acceleration of SAT-Based ATPG for Industrial Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unifying functional and parametric timing verification
Proceedings of the great lakes symposium on VLSI
Functional timing analysis made fast and general
Proceedings of the 49th Annual Design Automation Conference
RTL analysis and modifications for improving at-speed test
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem because of the inherent computational cost, and because in practice false paths are not specified one full path at a time. Instead designers use generalized false paths, which represent a set of paths. For instance the SDC format (Synopsys Design Constraint) specifies false path exceptions using a "--from --through --to" syntax that applies on sets of pins, often using wildcards to denote these sets. This represents many (usually hundreds to thousands) actual full paths. This paper proposes a method to verify generalized false paths in a very efficient manner. It is shown to be about 10x faster than the current state-of-the-art, making false path verification an overnight task or less for multi-million gate designs.