Efficient identification of multi-cycle false path

Authors:
Kai Yang;Kwang-Ting Cheng
Affiliations:
University of California, Santa Barbara;University of California, Santa Barbara
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

Citing 6
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Abstract

Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing analysis problem by considering both single-cycle and multi-cycle operations. We give a precise definition of multi-cycle false paths and provide the necessary conditions for multi-cycle sensitizable paths. We then propose an efficient algorithm to identify multi-cycle false paths. By considering both single-cycle and multi-cycle false paths, we could derive a shorter clock period than that determined by existing methods. Finally, we propose an algorithm to compute the valid clock period and demonstrate the improvement in clock frequency by taking multi-cycle false paths into account.