Waiting false path analysis of sequential logic circuits for performance optimization

Authors:
Kazuhiro Nakamura;Kazuyoshi Takagi;Shinji Kimura;Katsumasa Watanabe
Affiliations:
Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara 630-0101, Japan
Venue:
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Year:
1998

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