Automated multi-cycle symbolic timing verification of microprocessor-based designs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Waiting false path analysis of sequential logic circuits for performance optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Functionally Testable Path Delay Faults on a Microprocessor
IEEE Design & Test
Enhancing the performance of multi-cycle path analysis in an industrial setting
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient identification of multi-cycle false path
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fixed points for multi-cycle path detection
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper proposes a fast multi-cycle path analysis method for large sequential circuits. It determines whether or not all the paths between every flip-flop pair are multi-cycle paths. The proposed method is based on ATPG techniques, especially on implication techniques, to utilize circuit structure and multi-cycle path condition directly. The method also checks whether or not the multi-cycle path may be invalidated by static hazards in combinational logic parts. Experimental results show that our method is much faster than conventional ones.