Multi-clock path analysis using propositional satisfiability

Authors:
Kazuhiro Nakamura;Shinji Maruoka;Shinji Kimura;Katsumasa Watanabe
Affiliations:
Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama, Ikoma, Nara, 630-0101, Japan
Venue:
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Year:
2000

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fixed points for multi-cycle path detection

Proceedings of the Conference on Design, Automation and Test in Europe

Hi-index	0.00