Application Specific Worst Case Corners Using Response Surfaces and Statistical Models
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Efficient computation of the worst-delay corner
Proceedings of the conference on Design, automation and test in Europe
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, which work by propagating delay distributions, do not conform to modern design methodology. Instead, new statistical techniques are needed to modify corner analysis in ways that overcome its weaknesses without violating usage models of timing tools in modern flows.