Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Impedance characteristics of power distribution grids in nanoscale integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Speedpath prediction based on learning from a small set of examples
Proceedings of the 45th annual Design Automation Conference
A microarchitecture-based framework for pre- and post-silicon power delivery analysis
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Verification and codesign of the package and die power delivery system using wavelets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power grid analysis using random walks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
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Power grids with die-scale dimensions operate in a transient manner that is difficult to predict compared to larger power grids. Given a single excitation and a detailed model one can come to understand the dynamic effects occurring inside the die in terms of localized voltage droop scenarios. However, a major portion of understanding on-die power grids has to do with modeling the current stimulus pre-silicon for design purposes as well as generating a set of activities (via instructions) post-silicon in order to excite the worst case voltage droop. Any chip, especially a microprocessor, contains so many potential state transitions that it is not possible to simulate or enumerate all of them. A spectral-based learning and optimization method can alleviate this problem pre-silicon, while a micro-architectural based test generation scheme can help alleviate the problem post silicon.