Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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Proceedings of the 39th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Interval-valued reduced order statistical interconnect modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
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Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk aggressor alignment induced interconnect delay variation in a piecewise-quadratic function, and present closed form formulas for statistical interconnect delay calculation with crosstalk aggressor alignment variation. Our proposed method can be easily integrated in a statistical timer, where traditional corner-based timing windows are replaced by probabilistic distributions of crosstalk aggressor alignment, which can be refined by similar delay calculation iterations. Runtime is O(N) for initial delay calculation of N sampling crosstalk aggressor alignments, while pdf propagation and delay updating requires constant time. We compare with SPICE Monte Carlo simulations on Berkeley predictive model 70nm global interconnect structures and 130nm industry design instances. Our experimental results show that crosstalk aggressor alignment oblivious statistical delay calculation could lead to up to 114.65% (71.26%) mismatch of interconnect delay means (standard deviations), while our method gives output signal arrival time means (standard deviations) within 2.09% (3.38%) of SPICE Monte Carlo simulation results.