High level profiling based low power synthesis technique

Authors:
S. Katkoori;N. Kumar;R. Vemuri
Affiliations:
-;-;-
Venue:
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Year:
1995

Citing 0
Cited 2

Simulation based architectural power estimation for PLA-based controllers

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Simultaneous scheduling, allocation, binding, re-ordering, and encoding for crosstalk pattern minimization during high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

We present a profiling based technique for power estimation. This technique is implemented in the PDSS (Profile Driven Synthesis System) for the synthesis of low power designs. Initially, each module in the module library is characterized for the average switching capacitance per input vector. The input description is simulated using user-specified set of input vectors to collect the profile data for various operators and carriers. The profile data, in conjunction with the pre-characterized module library is used to estimate the total capacitance switched by each of the valid schedules produced by the PDSS scheduler. A valid schedule is one which satisfies other constants such as area and delay. The schedule with the least switching capacitance estimate is further synthesized to the layout level. Results show an average deviation of 12% compared with the actual switching capacitance values at the layout level.