Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects

Authors:
C. J. Akl;M. A. Bayoumi
Affiliations:
The Center for Adv. Comput. Studies, Louisiana at Lafayette Univ., LA;The Center for Adv. Comput. Studies, Louisiana at Lafayette Univ., LA
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

Citing 0
Cited 3

Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Transition skew coding for global on-chip interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous scheduling, allocation, binding, re-ordering, and encoding for crosstalk pattern minimization during high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Global signaling is becoming more and more challenging as technology scales down toward the deep submicron. We propose a new bus encoding technique, transition skew coding, that targets many of the global interconnects challenges such as crosstalk, peak energy and current, switching and leakage power, repeaters area, wiring area, signal integrity and noise. Simulations are done on different bus lengths using a 90nm library. Repeaters sizing and spacing are optimized, and the proposed encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy and area with low encoding and decoding latency overhead.