Interconnect synthesis and planning for high-performance ic designs
Interconnect synthesis and planning for high-performance ic designs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pulse width modulation for reduced peak power full-swing on-chip interconnect
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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This paper presents new simulation results of the previously proposed Transition Skew Coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal integrity, and wiring and repeater area minimization.