Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count

Authors:
Charbel J. Akl;Magdy A. Bayoumi
Affiliations:
University of Louisiana at Lafayette, Lafayette, LA, USA;University of Louisiana at Lafayette, Lafayette, LA, USA
Venue:
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Year:
2008

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Abstract

Achieving high-speed signaling across narrow deep-submicron wires with reduced repeater count is a major design challenge. A clocked repeater circuit, called assumer, that allows high-speed point-to-point signaling with single repeater per single-cycle wirelength is presented in this paper. Simulations at the 90-nm node on 3-mm to 10-mm range of wirelength considering minimum pitch intermediate and global metal layers show up to 31% delay reduction and up to 80% less repeater count compared to conventional repeated wires. However, assumer interconnect suffers from switching power overhead. Therefore, the proposed method is only suitable for designs where speed and area are the primary concerns.