Approaches to run-time and standby mode leakage reduction in global buses
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Self-timed regenerators for high-speed and low-power on-chip global interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a new receiver to reduce the number of repeaters used in global wiring. The receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Using the TAGS receiver we can run a 15mm line (180nm node) at 800 MHz with no repeaters. The same line requires three repeaters with a traditional receiver and consumed more power and area. The TAGS receiver also outperforms a standard inverter at the 70nm technology node. A noise analysis at the two technology nodes shows that the receiver maintains good functional noise immunity.