Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Transition Aware Global Signaling (TAGS)
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Interconnect accelerating techniques for sub- 100-nm gigascale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Self-Time Regenerators for High-Speed and Low-Power Interconnect
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pulse width modulation for reduced peak power full-swing on-chip interconnect
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%.