Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs

Authors:
Hariharan Sankaran;Srinivas Katkoori
Affiliations:
-;-
Venue:
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Year:
2009

Citing 0
Cited 2

Simultaneous scheduling, allocation, binding, re-ordering, and encoding for crosstalk pattern minimization during high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC

Microelectronics Journal

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Abstract

The Scalable Communications Core (SCC) is a flexible baseband processor that consists of a heterogeneous set of coarse-grained, programmable accelerators connected via a packet-based 3-ary 2-cube Network-on-Chip (NoC). SCC supports multiple wireless ...