RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A crosstalk-aware timing-driven router for FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Refining switching window by time slots for crosstalk noise calculation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Interconnect parasitic effects are one of the limiting factors for the performances of deep submicron VLSI designs, where the interconnect induced delay dominates over the gate delay. Furthermore, as coupling capacitance between wires increases due to the geometry scaling, the design verification process must accurately take into account crosstalk induced effects.In this paper, we describe CASTA (Crosstalk Aware Static Timing Analysis), a new efficient and accurate methodology for the timing performance verification of large VLSI designs, which accurately considers the crosstalk induced delay and noise injection. Our approach is based on the combination of Static Timing Analysis (STA) with interconnect network order reduction macromodeling techniques and it allows to evaluate the crosstalk effects during gate-level delay calculation, thus enlightening potential timing hazards.The timing effects due to the crosstalk between adjacent interconnects are accounted by a order reduction based macromodel of the overall linear interconnect network. The effectiveness of the proposed methodology has been demonstrated with the analysis of the crosstalk effects on a 0.25mm, high density, CMOS technology.