A Bus Encoding Technique for Power and Cross-talk Minimization

Authors:
P. Subrahmanya;R. Manimegalai;V. Kamakoti;Madhu Mutyam
Affiliations:
-;-;-;-
Venue:
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Year:
2004

Citing 0
Cited 8

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Optimal memoryless encoding for low power off-chip data buses

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Selective shielding: a crosstalk-free bus encoding technique

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Selective shielding technique to eliminate crosstalk transitions

ACM Transactions on Design Automation of Electronic Systems (TODAES)
A data capturing method for buses on chip

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Scalable codeword generation for coupled buses

Proceedings of the Conference on Design, Automation and Test in Europe
Simultaneous scheduling, allocation, binding, re-ordering, and encoding for crosstalk pattern minimization during high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fibonacci codes for crosstalk avoidance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

Considerable research has been done in the areaof bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, butnot both together. We propose No Adjacent Transition(NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminatescross-talk. NAT-encoding and decoding algorithms areproposed and an analytical study of power dissipation ispresented.