Two-dimensional compaction by “zone refining”

Authors:
Hyunchul Shin;Alberto L. Sangiovanni-Vincentelli;Carlo H. Séquin
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

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Abstract

A new technique for 2-dimensional layout compaction of integrated circuits is presented. After a traditional one-dimentional precompaction step, the size of the layout is further reduced with a technique that bears a strong similarity to the technique of 'zone-refining' used in the purification of crystal ingots. Individual circuit components or small clusters of components are peeled off row by row from the precompacted layout, moved across an open zone, and reassembled at the other end of this zone in a denser configuration. In this process both coordinates of the moved components are altered and jogs are introduced in the connecting wires between them to produce the needed flexibility for placing components into optimal positions. The constraint graphs in both the x- and y-direction are used and updated concurrently.