Data structures and network algorithms
Data structures and network algorithms
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A two-dimensional topological compactor with octagonal geometry
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
CACTUS: a symbolic CMOS two-dimensional compactor
EURO-DAC '90 Proceedings of the conference on European design automation
Two-Dimensional Layout Migration by Soft Constraint Satisfaction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
| Hi-index | 0.00 |
A new heuristic two-dimensional symbolic layout-compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce the layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bounded by &Ogr;(T1), where T1 is the run time of a typical one-dimensional compactor.