An efficient two-dimensional layout compaction algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Proceedings of the 1997 international symposium on Physical design
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Application of automated design migration to alternating phase shift mask design
Proceedings of the 2001 international symposium on Physical design
Monte Carlo Methods for 2-D Compaction
Monte Carlo Methods for 2-D Compaction
Calligrapher: A New Layout Migration Engine Based on Geometric Closeness
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Automatic process migration of datapath hard IP libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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Layout migration has re-emerged as an important task due to the increasing use of library hard intellectual properties. While recent advances of migration tools have accommodated new metrics, the underlying engine is based on the one-dimensional (1-D) layout compaction algorithm, largely due to its efficiency compared to its two-dimensional (2-D) counterpart. In this paper, we propose a new method that can overcome the artificial constraints introduced by the 1-D compaction algorithm, thereby effectively achieving the quality of 2-D compaction, yet keeping the computational cost almost as low as 1-D compaction. Our method is based on the application of soft constraints, or artificial constraints that are initially relaxed, and gradually tightened to be satisfied. We demonstrate the effectiveness of our approach by successfully solving the difficult 1-D compaction instances we found in the migration of Berkeley low power library, originally developed for 1.2um MOSIS process, into TSMC 0.25um and 0.18um technology.