Cell-based hierarchical pitchmatching compaction using minimal LP
DAC '93 Proceedings of the 30th international Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On the complexity of orthogonal compaction
Computational Geometry: Theory and Applications
Optimal Compaction of Orthogonal Grid Drawings
Proceedings of the 7th International IPCO Conference on Integer Programming and Combinatorial Optimization
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An algorithm for optimal two-dimensional compaction of VLSI layouts
Integration, the VLSI Journal
Interconnect bundle sizing under discrete design rules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
IEEE Spectrum
C5M-a control-logic layout synthesis system for high-performance microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Planar CMOS to multi-gate layout conversion for maximal fin utilization
Integration, the VLSI Journal
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Fueled by Moore's Law, VLSI market competition and economic considerations dictates the introduction of new processor's microarchitecture in a two-year cycle called ''Tick-Tock'' marketing strategy. A new processor is first manufactured in the most advanced stable process technology, followed in a one-year delay by introducing chips comprising same microarchitecture but manufactured in a newer scaled process technology, thus allowing higher production volumes, better performance and lower cost. Tick-Tock is enabled by the automation of chip's layout conversion from an older into a newer manufacturing process technology. This is a very challenging computational task, involving billions of polygons. We describe an algorithm of a hierarchy-driven optimization method for cell-based layout conversion used at Intel for already several product generations. It transforms the full conversion problem into successive problems of significantly smaller size, having feasible solutions if and only if the full-chip problem does. The proposed algorithm preserves the design intent, its uniformity and maintainability, a key for the success of large-scale projects.