Computational geometry: an introduction
Computational geometry: an introduction
Introduction to algorithms
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast algorithm for polygon decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Calligrapher: a new layout-migration engine for hard intellectual property libraries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-based interconnect migration by hierarchical optimization
Integration, the VLSI Journal
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Multi-gate transistors enable the pace of Moore's Law for another decade. In its 22nm technology node Intel switched to multi-gate transistors called TriGate, whereas IBM, TSMC, Samsung and others will do so in their 20nm and 14nm nodes with multi-gate transistors called FinFET. Several recent publications studied the drawing of multi-gate transistors layout. Designing new VLSI cell libraries and blocks requires massive re-drawing of layout. Hard-IP reuse is an alternative method taking advantage of existing source layout by automatically mapping it into new target technology, which was used in Intel's Tick-Tock marketing strategy for several product generations. This paper presents a cell-level hard-IP reuse algorithm, converting planar transistors to multi-gate ones. We show an automatic, robust transformation of bulk diffusion polygons into fins, while addressing the key requirements of cell libraries, as maximizing performance and interface compatibility across a variety of driving strength. We present a layout conversion flow comprising time-efficient geometric manipulations and discrete optimization algorithms, while generating manually drawn layout quality. Those can easily be used in composing larger functional blocks.