FinFETs for nanoscale CMOS digital integrated circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Spacer defined FinFET: Active area patterning of sub-20nm fins with high density
Microelectronic Engineering
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FinFETs and Other Multi-Gate Transistors
FinFETs and Other Multi-Gate Transistors
Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Can pin access limit the footprint scaling?
Proceedings of the 49th Annual Design Automation Conference
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Planar CMOS to multi-gate layout conversion for maximal fin utilization
Integration, the VLSI Journal
Ultra-low leakage arithmetic circuits using symmetric and asymmetric finFETs
Journal of Electrical and Computer Engineering
| Hi-index | 0.00 |
In this paper, issues related to the physical design and layout density of FinFET standard cells are discussed. Analysis significantly extends previous analyses, which considered the simplistic case of a single FinFET device or extremely simple circuits. Results show that analysis of a single device cannot predict the layout density of FinFET cells, due to the additional spacing constraints imposed by the standard cell structure. Results on the layout density of FinFET standard cell circuits are derived by building and analyzing various cell libraries in 32-nm technology, based on three-terminal (3T) and four-terminal (4T) devices, as well as on the recently proposed cells with mixed 3T-4T devices (MT). The results obtained for spacer- and lithography-defined FinFETs are observed from the technology scaling perspective by also considering 45- and 65-nm libraries. The effect of the fin and cell height on the layout density is studied. Results show that 3T and MT FinFET standard cells can have the same layout density as bulk cells (or better) for low (moderate) fin heights. Instead, 4T standard cells have an unacceptably worse layout density. Hence, MT standard cells turn out to be the only viable option to apply back biasing in FinFET standard cell circuits.