Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.