Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors

Authors:
Sreehari Veeramachaneni;Kirthi M. Krishna;Lingamneni Avinash;Sreekanth Reddy Puppala;M. B. Srinivas
Affiliations:
International Institute of Information Technology;International Institute of Information Technology;International Institute of Information Technology;International Institute of Information Technology;International Institute of Information Technology
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and designs of high speed, low power 3- 2, 4-2 and 5-2 compressors capable of operating at ultra-low voltages are presented. The power consumption, delay and area of these new compressor architectures are compared with existing and recently proposed compressor architectures and are shown to perform better. The proposed architecture lays emphasis on the use of multiplexers in arithmetic circuits that result in high speed and efficient design. Also in all existing implementations of XOR gate and multiplexers, both output and its complement are available but current designs of compressors do not use these outputs efficiently. In the proposed architecture these outputs are efficiently utilized to improve the performance of compressors. The combination of low power, low transistor count and lesser delay makes the new compressors a viable option for efficient design.