Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors

Authors:
Cláudio Machado Diniz;João Altermann;Eduardo Costa;Sergio Bampi
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Universidade Católica de Pelotas, Pelotas, Brazil;Universidade Católica de Pelotas, Pelotas, Brazil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Venue:
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Year:
2010

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Abstract

Adder compressors have already been proved as efficient structures to reduce the critical path of adder-tree circuits with large number of input values. Our recently proposed intra-frame prediction hardware architecture for H.264/AVC video encoder employs adder-tree circuits for SAD (Sum of Absolute Difference) calculation and for the intra prediction itself. In this work, we propose the improvement of our intra-frame prediction hardware architecture by using efficient 4-2 and 5-2 adder compressors for the SAD (Sum of Absolute Difference) calculation and plane mode sample prediction stages, instead of using common adder operators from standard-cells library, to reduce the critical combinational path of the entire architecture. Synthesis results on TSMC 0.18/m standard-cells show that the intra-frame prediction architecture, using the adder compressors, achieves 33% frequency increase when compared with the original architecture. These results herein presented show that it is possible to obtain higher performance in our architecture by using the adder compressors in both the SAD and the plane mode intro prediction, since these modules contain the critical path of the architecture. With these results the architecture is able to support real-time encoding of HD 1080p digital videos at 63 frames/s.