A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video

Authors:
Cláudio Machado Diniz;Bruno Zatt;Luciano Agostini;Altamiro Susin;Sergio Bampi
Affiliations:
GME, PGMICRO, PPGC, Informatics Institute, UFRGS, Porto Alegre, RS, Brazil;GME, PGMICRO, PPGC, Informatics Institute, UFRGS, Porto Alegre, RS, Brazil;UFPel, Pelotas, RS, Brazil;GME, PGMICRO, PPGC, Informatics Institute, UFRGS, Porto Alegre, RS, Brazil;GME, PGMICRO, PPGC, Informatics Institute, UFRGS, Porto Alegre, RS, Brazil
Venue:
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Year:
2009

Citing 3
Cited 1

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Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

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Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors

SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design

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Abstract

This work presents an intra frame prediction hardware architecture for H.264/AVC baseline/main profile encoder which performs real time processing of HDTV 1080p videos. It is achieved by exploring the parallelism of intra prediction and by reducing the latency for Intra 4×4 processing, which is the intra encoding bottleneck. Synthesis results on Xilinx Virtex-II Pro FPGA and TSMC 0.18µm standard-cells indicate that this architecture is able to real time encode HDTV 1080p video operating at 110 MHz. Our architecture can encode HD1080p, 720p and SD video in real time at a frequency 25% lower when compared to similar works.