A unified systolic architecture for combined inter and intra predictions in H.264/AVC decoder
Proceedings of the 2006 international conference on Wireless communications and mobile computing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm
Proceedings of the conference on Design, automation and test in Europe
Low-power H.264/AVC baseline decoder for portable applications
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A fast intra prediction algorithm for H.264/AVC video coding
ISPRA'08 Proceedings of the 7th WSEAS International Conference on Signal Processing, Robotics and Automation
A Fast Hybrid Decision Algorithm for H.264/AVC Intra Prediction Based on Entropy Theory
MMM '09 Proceedings of the 15th International Multimedia Modeling Conference on Advances in Multimedia Modeling
A Performance Optimized Architecture of Deblocking Filter in H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec
IEICE - Transactions on Information and Systems
A 140-MHz 94 K gates HD1080p 30-frames/s intra-only profile H.264 encoder
IEEE Transactions on Circuits and Systems for Video Technology
Intra-predictive transforms for block-based image coding
IEEE Transactions on Signal Processing
Efficient MB and prediction mode decisions for intra prediction of H.264 high profile
PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
Fast H.264 selective intra mode decision for inter-frame coding
PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
A dynamic quality-adjustable H.264 video encoder for power-aware video applications
IEEE Transactions on Circuits and Systems for Video Technology
Efficient intra mode decision via statistical learning
PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
Optimization of spatial error concealment for H.264 featuring low complexity
MMM'08 Proceedings of the 14th international conference on Advances in multimedia modeling
Towards a comprehensive RVC VTL: a CAL description of an efficient AVC baseline encoder
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
Microprocessors & Microsystems
Video transcoding to support random access in scalable video coding
WSEAS Transactions on Signal Processing
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Proceedings of the Conference on Design, Automation and Test in Europe
MMM'11 Proceedings of the 17th international conference on Advances in multimedia modeling - Volume Part I
An efficient architecture for H.264 intra prediction mode decision algorithm
NEHIPISIC'11 Proceeding of 10th WSEAS international conference on electronics, hardware, wireless and optical communications, and 10th WSEAS international conference on signal processing, robotics and automation, and 3rd WSEAS international conference on nanotechnology, and 2nd WSEAS international conference on Plasma-fusion-nuclear physics
CAL Dataflow Components for an MPEG RVC AVC Baseline Encoder
Journal of Signal Processing Systems
Computational time reduction using low complexity skip prediction for H.264/Avc standard
DNCOCO'06 Proceedings of the 5th WSEAS international conference on Data networks, communications and computers
A power-efficient and self-adaptive prediction engine for H.264/AVC decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Journal of Visual Communication and Image Representation
Computation and power reduction techniques for H.264 intra prediction
Microprocessors & Microsystems
Fully utilized and low design effort architecture for H.264/AVC intra predictor generation
MMM'10 Proceedings of the 16th international conference on Advances in Multimedia Modeling
1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation
Journal of Signal Processing Systems
Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels--A Showcase
Journal of Signal Processing Systems
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
Journal of Signal Processing Systems
Journal of Signal Processing Systems
An H.264 Quad-FullHD low-latency intra video encoder
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized Hardware Implementation for Forward Quantization of H.264/AVC
Journal of Signal Processing Systems
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Intra prediction with rate-distortion constrained mode decision is the most important technology in H.264/AVC intra frame coder, which is competitive with the latest image coding standard JPEG2000, in terms of both coding performance and computational complexity. The predictor generation engine for intra prediction and the transform engine for mode decision are critical because the operations require a lot of memory access and occupy 80% of the computation time of the entire intra compression process. A low cost general purpose processor cannot process these operations in real time. In this paper, we proposed two solutions for platform-based design of H.264/AVC intra frame coder. One solution is a software implementation targeted at low-end applications. Context-based decimation of unlikely candidates, subsampling of matching operations, bit-width truncation to reduce the computations, and interleaved full-search/partial-search strategy to stop the error propagation and to maintain the image quality, are proposed and combined as our fast algorithm. Experimental results show that our method can reduce 60% of the computation used for intra prediction and mode decision while keeping the peak signal-to-noise ratio degradation less than 0.3 dB. The other solution is a hardware accelerator targeted at high-end applications. After comprehensive analysis of instructions and exploration of parallelism, we proposed our system architecture with four-parallel intra prediction and mode decision to enhance the processing capability. Hadamard-based mode decision is modified as discrete cosine transform-based version to reduce 40% of memory access. Two-stage macroblock pipelining is also proposed to double the processing speed and hardware utilization. The other features of our design are reconfigurable predictor generator supporting all of the 13 intra prediction modes, parallel multitransform and inverse transform engine, and CAVLC bitstream engine. A prototype chip is fabricated with TSMC 0.25-μm CMOS 1P5M technology. Simulation results show that our implementation can process 16 mega-pixels (4096×4096) within 1 s, or namely 720×480 4:2:0 30 Hz video in real time, at the operating frequency of 54 MHz. The transistor count is 429 K, and the core - size is only 1.855×1.885 mm2.