A 140-MHz 94 K gates HD1080p 30-frames/s intra-only profile H.264 encoder
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
IEEE Transactions on Circuits and Systems for Video Technology
Fast mode decision algorithm for intraprediction in H.264/AVC video coding
IEEE Transactions on Circuits and Systems for Video Technology
A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction
IEEE Transactions on Circuits and Systems for Video Technology
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Video applications are moving from Full-HD capability (1920x1080) to even higher resolutions such as Quad-FullHD (3840x2160). The H.264 Intra-mode can be used by embedded devices to trade off the better encoding efficiency of H.264 temporal prediction (Inter-mode) against savings in area and power as well as saving the massive computational overhead of the sub-pixel motion estimation by using only spatial prediction (Intra-mode). Still, the H.264 Intra-mode requires a large computational effort and imposes severe challenges when targeting Quad-FullHD 25 fps real-time video encoding at moderate operating frequencies (we target 150 MHz) and limited area budget. Therefore, in this work we address the strong sequential data dependencies within H.264 Intra-mode that restrict the parallelism and inhibit high resolution encoding by a) decoupling of DC and AC transform paths, b) cycle-budget aware mode prediction scheduling while c) being area efficient. Using our proposed techniques, Quad-FullHD (3840x2160) 28 fps video encoding is achieved at 150 MHz, making our architecture applicable for high definition recording.