A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction

Authors:
Jia-Ching Wang;Jhing-Fa Wang;Jar-Ferr Yang;Jang-Ting Chen
Affiliations:
Nat. Cheng Kung Unvi., Tainan;-;-;-
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
2007

Citing 0
Cited 12

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Efficient MB and prediction mode decisions for intra prediction of H.264 high profile

PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
Fast H.264 selective intra mode decision for inter-frame coding

PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
Efficient mode selection with BMA based pre-processing algorithms for H.264/AVC fast intra mode decision

MMM'11 Proceedings of the 17th international conference on Advances in multimedia modeling - Volume Part I
Algorithm and hardware design of a fast intra-frame mode decision module for h.264/AVC encoders

Proceedings of the 24th symposium on Integrated circuits and systems design
A fast intra prediction mode decision using DCT and quantization for H.264/AVC

Image Communication
Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems

Journal of Visual Communication and Image Representation
Low-complexity hierarchical mode decision algorithms targeting VLSI architecture design for the H.264/AVC video encoder

VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
A fast two-step block type decision algorithm for intra prediction in H.264/AVC high profile

Multimedia Tools and Applications
Algorithm and hardware design of a fast intra frame mode decision module for H.264/AVC encoders

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
An H.264 Quad-FullHD low-latency intra video encoder

Proceedings of the Conference on Design, Automation and Test in Europe
135-MHz 258-K gates VLSI design for all-intra H.264/AVC scalable video encoder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the proposed fast intra-algorithm reduces 40% computation with slight peak signal-to-noise ratio (PSNR) degradation. The designed DES VLSI engine comprises a zigzag converter, a DES finite-state machine (FSM), and a DES core. The former two units handle memory allocation and control flow while the last performs pseudoblock computation, edge filtering, and dominant edge strength extraction. With semicustom design fabricated by 0.18 mum CMOS single-poly-six-metal technology, the realized die size is roughly 0.15 times 0.15 mm2 and can be operated at 66 MHz.