A 140-MHz 94 K gates HD1080p 30-frames/s intra-only profile H.264 encoder

Authors:
Yu-Kun Lin;Chun-Wei Ku;De-Wei Li;Tian-Sheuan Chang
Affiliations:
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan;Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan;Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan;Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Circuits and Systems for Video Technology
Year:
2009

Citing 4
Cited 8

A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Proceedings of the 17th ACM Great Lakes symposium on VLSI
A Configurable IP for Mode Decision of H.264/AVC Encoder

AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

IEEE Transactions on Circuits and Systems for Video Technology
A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications

IEEE Transactions on Circuits and Systems for Video Technology

Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors

SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
A Fast H.264 Intra Frame Encoder with Serialized Execution of 4 × 4 and 16 × 16 Predictions and Early Termination

Journal of Signal Processing Systems
Algorithm and hardware design of a fast intra-frame mode decision module for h.264/AVC encoders

Proceedings of the 24th symposium on Integrated circuits and systems design
Low-complexity hierarchical mode decision algorithms targeting VLSI architecture design for the H.264/AVC video encoder

VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder

Journal of Signal Processing Systems
Algorithm and hardware design of a fast intra frame mode decision module for H.264/AVC encoders

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
An H.264 Quad-FullHD low-latency intra video encoder

Proceedings of the Conference on Design, Automation and Test in Europe
135-MHz 258-K gates VLSI design for all-intra H.264/AVC scalable video encoder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a HD1080p 30-frames/s H.264 intra encoder operated at 140 MHz with just 94 K gate count and O.72-mm2 core area for digital video recorder or digital still camera applications. To achieve high throughput and low area cost for high-definition video, we apply the modified three-step fast intra prediction technique to reduce the cycle count while keeping the quality as close as full search. Then, in architecture scheduling, we further adopt the variable pixel parallelism instead of constant four-pixel parallelism to speed up performance on the critical intra prediction part while keeping other parts unchanged for low area cost. The achieved design only needs half of the working frequency and reduces the gate count cost by 23.5% compared with the previous design with the same HD720p 3O-frames/s requirement. Besides, our design at 140 MHz can support HD1080p 30 frames/s for digital video encoder or 4096 × 2304 images with 6.78 frames/s for digital still camera application.